Part 1: Technological Barriers – The Monopolized CPU Core Market
The foundational technology of global processor chips has long been dominated by two architectures:
x86: Dominates the PC and server markets, controlled by Intel and AMD.
ARM: Occupies the mobile and embedded sectors, covering over 90% of smart device chip designs through its "core licensing" model.
ARM’s licensing model consists of two types:
Core Licensing: Directly purchasing pre-designed CPU IP cores from ARM, a model most domestic manufacturers rely on.
Architecture Licensing: Limited to a few companies like Apple and Qualcomm, allowing them to design custom cores based on ARM’s instruction set.
For domestic manufacturers, the lack of core design capability results in technological dependence. The complexity of CPU core design is reflected in:
Instruction Set Compatibility: Requires deep adaptation with operating systems, compilers, and software ecosystems.
Microarchitecture Innovation: High technical barriers in pipeline design, power efficiency optimization, and multi-core scaling.
Beijing Ingenic initially adopted the MIPS instruction set due to its simplicity (high power efficiency) and flexible licensing model, enabling independent core design. Later, it transitioned to RISC-V, embracing open-source ecosystems to break ARM’s monopoly.
Part 2: Ingenic’s Core Evolution – From Embedded Leadership to RISC-V Breakthrough
From embedded benchmarks to intelligent upgrades, Ingenic’s core technology has continuously evolved, achieving breakthroughs in both performance and application scenarios:
1. XBurst1: A Milestone for Domestic Embedded Processors
Technological Breakthroughs:
Ultra-Low Power: 0.07mW/MHz, with a clock speed of up to 1GHz.
SIMD Acceleration: 128-bit parallel computing, improving multimedia efficiency.
Instruction Set Compatibility: Based on MIPS, allowing direct use of MIPS ecosystem toolchains.
2. XBurst2: A Multi-Core Engine for Intelligent Upgrades
Performance Leap:
Supports SMT (Simultaneous Multithreading) and SMP (Symmetric Multi-Processing), scaling up to 8 cores per cluster.
Performance Benchmark: 512-bit SIMD instructions deliver twice the performance of comparable ARM cores (e.g., Cortex-A55).
Application Expansion:
Targets high-compute fields like intelligent security and machine vision. For example, an industrial 3D printer using XBurst2 saw improved rendering efficiency and significantly reduced costs.
3.Victory Series: Independent Practice with RISC-V
Balancing Low Power and High Performance:
Victory0: Targets microcontrollers, competing with ARM Cortex-M; power consumption as low as 0.015mW/MHz, clocked at 500MHz.
Victory2: Features a dual-issue in-order architecture, rivaling ARM Cortex-A55.
Security and Flexibility:
Modular design supports AI acceleration extensions, adapting to fragmented IoT scenarios. For example, a smart home brand using Victory0 achieved significantly lower standby power consumption.
Part 3: Significance – From Following to Leading in Foundational Technology
Beijing Ingenic’s independent core design not only achieves performance breakthroughs but also validates its commercial viability through real-world applications:
Hybrid Architecture Practice: The Ingenic X2600 chip adopts a heterogeneous design combining XBurst2 (MIPS) + Victory0 (RISC-V), significantly improving energy efficiency for applications like printers and robots.
1. Performance Superiority
The XBurst series outperforms comparable ARM cores in PPA (Performance, Power, Area) metrics. For example, XBurst2’s AI instruction set is optimized for machine vision, delivering substantially higher computational efficiency in barcode recognition and image analysis.
2. Scenario Adaptation
Custom instruction sets for AI and IoT needs cover diverse fields like consumer electronics, industrial control, and smart vision. The Victory series RISC-V cores, with their modular design and low power consumption, are widely used in smart home gateways and industrial sensors, achieving mass-market penetration.
3. Supply Chain Security
From XBurst to Victory, Ingenic’s technology matrix reduces reliance on ARM cores. For example, its self-developed T-series chips, with hundreds of millions of shipments, have become a benchmark for independent core technology in intelligent security.
Conclusion
Through a three-step strategy of instruction set compatibility, microarchitecture innovation, and ecosystem migration, Beijing Ingenic has proven that domestic CPU cores can achieve independent breakthroughs. Its approach not only shatters the stereotype that "domestic chips can only follow" but also opens new opportunities in global open-source ecosystems like RISC-V. With continued core technology advancements, domestic chips are poised to transition from "replacement" to "leadership" in more fields.
This article is the first in the "Ingenic Technology Series".
Upcoming Previews:
Part 2: "Ecosystem Restructuring – The Code Behind the Transition from MIPS to RISC-V."
Part 3: "Paradigm Shift – The Leap from Technological Followership to Independent Leadership."
