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Ingenic CPU Technology

CPU technology, whether in the form of chip products or IP cores, has gradually been monopolized since the 1980s. In the computer field, Intel and AMD's X86 chips have dominated the market for over 30 years; in the field of CPU core licensing, ARM has basically monopolized the CPU IP core market since the beginning of this century, leveraging the success of smartphones. The Ingenic CPU design team has been working in the industry for many years, trying to carve out a new path under the monopoly of X86 and ARM. This is not just about designing better PPA (Performance, Power, Area), but also about providing a better computing architecture in response to the demands of AI and IoT. Ingenic's first attempt and achievement is the XBurst CPU technology based on the MIPS instruction set.

XBurst is based on the MIPS basic instruction set, and has expanded the DSA (Domain Specific Architecture) for multimedia and AI computing.

The microarchitecture design is unique, and its performance, power consumption, and size specifications far exceed those of the existing 32-bit CPU cores in the industry. At the same time, the DSA extended for multimedia and AI effectively supports applications such as multimedia and AI.

XBurst Series CPU Core (Based on MIPS Instruction Set)

Ingenic's first attempt and achievement is the XBurst CPU technology based on the MIPS instruction set. XBurst is based on the MIPS basic instruction set, and has expanded the DSA (Domain Specific Architecture) for multimedia and AI computing. The microarchitecture design is unique, and its performance, power consumption, and size specifications far exceed those of the existing 32-bit CPU cores in the industry. At the same time, the DSA extended for multimedia and AI effectively supports applications such as multimedia and AI.

	XBurst1	XBurst2
Base ISA	MIPS32 R5	MIPS32 R5
SIMD Extension	MXU2.0 - 128bits SIMD	MSA128 -128bits SIM DMXA128 - 128bits SIMD MXU3.0-512bits SIMD
Micro-Architecture	9 stage pipeline Single issue	Dual-Issue In-Order 2 Hardware Threads SM
Coremark	2.3	3.6 (single thread)
Power Consumption	0.07mW/MHz.40nm	0.13mW/MHz.28nm

Highlights

Leading energy efficiency ratio in the industry

High performance and low power consumption

The ultimate in terms of area.

DSA expansion for AI and multimedia

Specifications

Name

Specifications

XBurst1

-MIPS32 R5 ISA
-MXU2.0 128bit SIMD Extension
-Single issue
-9 state pipeline
-16~32KB L1 cache

XBurst2

-MIPS32 R5 ISA
-MSA128 SIMD Extension
-MXA128 SIMD Extension

-MXU3.0 512bit SIMD Extension

Data download

Burst1 CPU Core Programming Manual

Click to download

XBurst1 Instruction Set Architecture MIPS extension/enhanced Unit 2

Click to download

XBurst2 CPU Core Programming Manual

Click to download

XBurst Instruction Set Architecture MIPS eXtended Architecture Programming Manual

Click to download